1. Field of the Invention
The present invention relates to electrical circuitry and, in particular, to systems and methods for generating reference voltages.
2. Description of the Prior Art
Active matrix liquid crystal displays (AMLCDs) are currently the leading flat-panel display technology. An AMLCD comprises a grid (or matrix) of picture elements (pixels). Thousands or millions of these pixels are used together to create an image on such a display. In a thin film transistor (TFT) panel design, TFT technology is used to build a tiny transistor switch and capacitor for each pixel in the AMLCD panel. TFTs act as switches to individually turn each pixel “on” (light) or “off” (dark). Besides the normal display mode in which an image is represented with full gradation, a display usually has several power-saving modes. For example, a display can have an n-gradation mode (where n is an integer smaller than the number of levels in full gradation) in which an image is represented with fewer gradations, a partial display mode in which only a portion of the display is used to represent an image, and/or a standby mode in which the display is turned off temporarily until being activated again.
Integrating driving (reference voltage generating) circuits into display panels using TFT technology can largely reduce display module cost. In order to have precise analog voltage control and to simplify circuit structures in the integrated reference voltage generating circuits, a conventional resistor string (R-string) approach is adopted for providing different voltages. FIG. 1 shows a prior art reference voltage generating circuit 10 disclosed in U.S. Pat. No. 6,839,043 to Nakajima, which is incorporated herein by reference. The reference voltage generating circuit 10 includes switch circuits 41 and 42, dividing resistors R1-R7, and switches SW15 and SW16. The switch circuits 41 and 42 include switches SW11, SW12 and switches SW13, SW14, respectively. The switches SW11-SW14 couple output terminals A and B of the R-string to a positive power supply Vcc and a power supply Vss, which has a lower voltage level with respect to the positive power supply Vcc. The power supplies Vcc and Vss operate at fixed periods in opposite phases for row inversion driving methodology. The dividing resistors R1 to R7 are connected in series between output terminals A and B of the R-string, with switches SW15 and SW16 interposed therebetween, respectively. Voltages V0, V7, and V1-V6 obtained by voltage division by the R-string are outputted to a digital-analog-converter (DAC).
Reference is made to FIG. 2 for a timing chart illustrating the operation of the reference voltage generating circuit 10. In the reference voltage generating circuit 10 of FIG. 1, the reference voltages V0 and V7 are both produced by connecting node A to the positive power supply Vcc and node B to the power supply Vss in a first driving period, and by connecting node B to the positive power supply Vcc and node A to the power supply Vss in a second driving period. Each such driving period alternates in a fixed interval based on control pulses φ1 and φ2, as shown in the timing chart of FIG. 2. Meanwhile, the reference voltages V1-V6 for intermediate gradations are produced by voltage division through the dividing resistors R1 to R7. During power-saving modes, the switches SW15 and SW16 are opened (switched off) to stop the supply of current to the dividing resistors R1-R7 based on control pulse φ3. As a result, since no current flows through the dividing resistors R1-R7 and power consumption by the dividing resistors R1 to R7 is eliminated, a reduction of the power consumption can be anticipated. Although the voltage levels of V1 and V6 are represented with flat lines of zero voltage in FIG. 2 during power saving modes, the prior art reference voltage generating circuit 10 actually produces floating voltages when the R-string is disconnected from power supplies Vcc and Vss.
The prior art reference voltage generating circuit 10 has two perceived major drawbacks. First, the switches SW15 and SW16 are used to disconnect the R-string from the power sources Vcc and Vss during power-saving modes. In contrast to metal-oxide semiconductor field-effect transistors (MOSFETs), which are made on silicon wafers and use bulk-silicon as an active layer, a TFT is a transistor the active, current-carrying layer of which is a thin film (usually a film of polysilicon). Thus, the resistance of a TFT is usually much larger than that of a MOSFET. In order to achieve fast turn-on time and small voltage drop across switches for the reference voltage generating circuit 10, the switches SW15 and SW16 typically are large enough to exhibit low turn-on resistance. As a result, the reference voltage generating circuit 10 occupies a large amount of space. Second, since the R-string is disconnected from the power sources Vcc and Vss, the release voltage generating circuit 10 exhibits floating voltage levels that are outputted to the DAC during power-saving modes This tends to result in the DAC operation being non-stable and can result in more power consumption.